主要經歷（教育及工作經歷）：
1995年02月-1998年02月：上海交通大學電院 博士研究生
1998年02月-2000年06月🦵🏽🛷：浙江大學信電系 博士後
2000年06月-2003年06月：沐鸣娱乐專用集成電路與系統國家重點實驗室 博士後
2007年06月🙍🏻♀️：比利時微電子研究中心IMEC培訓學習
2003年06月-至今：沐鸣 教授
研究方向⚔️：
1）可編程芯片設計及其測試方法研究
2）基於FPGA的神經網絡加速器設計方法研究
3）基於SoC FPGA的深度學習研發平臺設計
4）嵌入式可編程 IP 核及其軟硬件設計方法研究
主講課程
“信號與通信系統 ” （本科生）
“集成電路設計基礎”（ 科碩研究生）
“VLSI系統設計導論”（工碩研究生）
“集成電路設計透視” （書院課程)
榮譽和獎勵：
上海市巾幗創新獎🎖，2007
適用於數據通路應用的可編程邏輯器件及其軟件系，獲高等學校科技進步二等獎（2），頒證（獎）單位🚵🏽♀️：中華人民共和國教育部🫲🏽，2007
年度微電子研究院先進個人獎，2007
年度沐鸣獎教金二等獎，2008
近期發表論文：
1.Xiong, Wei🌮，Lai, Jinme，An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique，Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI，2022，275-280
2.Qingliang Liu, Jinmei Lai, Jiabao Gao. An Efficient Channel-Aware Sparse Binarized Neural Networks inference Accelerator, IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(3): 1637-1641.
3.Jiabao Gao, Qingliang Liu and Jinmei Lai. An Approach of Binary Neural Network Energy-Efficient Implementation, Electronics, 2021,10(15), 1380. (IF為2.397 )
4.Jiabao Gao, Yuchen Yaoi, and Jinmei Lai. FCA-BNN Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA, IEICE transaction on information and system, 2021, E104.D(8): 1367-1377.
5.Qingliang Liu, Jiabao Gao, Jinmei Lai. TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021: 1-5.
6.Zhengjie Li, Jiabao Gao, Jinmei Lai. HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure, IEICE Transactions on Information and Systems, 2021, E104.D(10): 1724-1733.
7.Qingliang Liu, Jinmei Lai, Stochastic Loss Function, AAAI Conference on Artificial Intelligence (AAAI2020)
8.Chengyu Hu, Peng Lu, Meng Yang, Jian Wang, Jinmei Lai, A SA-based parallel method for FPGA placement, IEICE Electronics Express, 2018-12-25，Volume 15, Issue 24, Pages 20180943.
9.Jiabao. Gao, Jian Wang, M. T. Arafin, Jinmei Lai. FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs, 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 2020: 207-212.
10.Lu Z Y, Liu J F, Pang Y B , et al. A Low-delay Configurable Register for FPGA[C]// 2019 IEEE 13th International Conference on ASIC (ASICON). IEEE, 2019.
11.Yunbing Pang, Jiqing Xu, Yufan Zhang, Xinxuan Tao*, Jian Wang, Meng Yang, Jinmei Lai*👦🏿，Research on Circuit-Level Design of High Performance and Low Power FPGA Interconnect Circuits in 28nm Process，ICSICT 2018，2018 IEEE 14th International Conference on Solid-State and Integrated Circuit Technology, Oct.31-Nov. 3,2018,Qingdao,China
12.Zhen Yang, Chuanzeng Liang, Jian Wang, and Jinmei Lai ,Testing Modern FPGA Local Interconnects Based On Repeatable Configuration Modules, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016)
13.Yuanlong Xiao, Jian Wang, and Jinmei Lai，A Universal Automatic On-Chip Measurement of FPGA's Internal Setup and Hold Times🚔，IEICE Electronics Express, Publicized December 10, 2016
14.Xu Hanyang，Lai Jinmei，A FPGA Prototype Design Emphasis on Low Power Technique，FPGA2014, Proceedings of the 2014 ACM/SIGDA International Symposium on Field Programmable Gate Array, Monterey California,USA
15.Chun Zhu, Jian Wang, Jinmei Lai，A Novel Net-Partition-Based Multithread FPGA Routing Method，23rd international conference on field programmable logic and applications,FPL 2013 , Porto,Portugal,Sept.2-4,2013,oral
16.Hanyang Xu, Jian Wang, and Jinmei Lai，Prototyping design of a flexible DSP block with pipeline structure for FPGA，IEICE Electronics Express,Publicized August 19, 2016
17.Wen Yu，Jin-mei Lai，A Fully Digital DLLs Integrated in FPGAs🧚♀️，ICSICT 2008🏊🏿♂️，The 9th International Conference on Solid-State and Integrated-Circuit Technology🚗🍢，October 20-23, 2008,Beijing Jingyi Hotel, Beijing, China
