歡迎本科生👷🏿、碩博研究生🤾🏻‍♀️🕺、博士後加入課題組🏄🏻‍♀️。提供全面的芯片開發環境，包括設計、流片🤘、測試等關鍵流程。給予系統性的學術訓練以及良好融洽的團隊氛圍👽。有興趣者請郵件聯系🤸🏻‍♂️🔠。

研究方向：

1🧓🏼、面向關鍵安全型應用的高可靠智能算法與專用加速芯片🛁：

　　此方向專註於研究適用於關鍵安全型應用的高可靠智能算法及其芯片實現🧕🏻。研究內容涵蓋星上智能處理🪐、自動駕駛系統、機器人控製技術等多個領域。通過構建高度可靠的算法和芯片🧛🏿‍♂️，致力於提升關鍵應用的安全性和智能化水平，確保關鍵系統的穩定運行和數據安全🚀。

2、面向商業航天低成本要求的集成電路加固技術🖐🏻🔮：

　　該研究方向聚焦於商業航天領域中集成電路的加固技術🏄🏿，旨在通過電路設計提高集成電路的可靠性與耐用性🚳，同時最大化降低成本開銷🏋️‍♀️，包括芯片“硬成本”以及開發周期“時間成本”。

教育背景：

沐鸣娱乐🫁，微電子學與固體電子學💁🏿‍♂️👨🏻‍🚒，博士 （導師：曾曉洋教授）

卡爾斯魯厄理工沐鸣（德國），電子工程🗣🦦，聯合培養博士 （導師：Prof. Mehdi Tahoori）

工作學術經歷：

2024年09月 - 至今 沐鸣，青年研究員

2022年02月 - 2024年08月 沐鸣，博士後/助理研究員

人才稱號：

上海市浦江人才 2022

學術兼職：

CCF容錯計算專委會執行委員

代表性成果：

[1] Yan Li, Chao Chen, Xu Cheng, Jun Han, and Xiaoyang Zeng, “DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 4015–4027, 2023, doi: 10.1109/TCSI.2023.3302341.

[2] Yan Liu, Yan Li, Xu Cheng, Jun Han, and Xiaoyang Zeng, “A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 4, pp. 1639–1648, Apr. 2023, doi: 10.1109/TCSI.2023.3237706.

[3] Chenyu Zhang, Yan Li, Xu Cheng, Jun Han, and Xiaoyang Zeng. “Impact of Tap Cell on Single Event Transient in 28-nm CMOS Technology.” 2022 European Conference on Radiation and its Effects on Components and Systems (RADECS), 2022.

[4] Chiyu Tan, Yan Li, Xu Cheng, Jun Han, and Xiaoyang Zeng. “Pulse Quenching Effect Characterized by Inverter Chains under Heavy-ion Irradiation in 28-nm CMOS Technology.” 2022 European Conference on Radiation and its Effects on Components and Systems (RADECS), 2022.

[5] Chiyu Tan, Yan Li, Xu Cheng, Jun Han, and Xiaoyang Zeng, “General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 68, no. 7, pp. 3044–3057, Jul. 2021.

[6] Yan Li, Jun Han, Xiaoyang Zeng, and Mehdi B. Tahoori, “TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications,” in 2021 Design, Automation Test in Europe Conference Exhibition (DATE), Feb. 2021.

[7] Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, and Xiaoyang Zeng. “Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit,” in 2020 57th ACM/IEEE Design Automation Conference (DAC), Jul. 2020.

[8] Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B.  Tahoori, and Xiaoyang Zeng, “A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 67, no. 9, pp. 1619–1623, Sep. 2020.

[9] Yan Li, Jun Han, XiaoyoungZeng, and Xiaoyang Zeng. “A Multi-Objective Optimization Framework to Design Soft-Error-Immune Circuit.” 2019 European Conference on Radiation and its Effects on Components and Systems(RADECS), 2019.